1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array having a hierarchical bit line structure.
2. Description of Related Art
In recent years, miniaturization of semiconductor memory devices such as DRAM has been achieved, and thus semiconductor devices comprising a memory cell array in which bit lines and sense amplifiers are hierarchized have been proposed (for example, see Patent References 1 to 4 and Non-Patent Reference 1). For example, FIG. 3 of Patent Reference 1 shows a DRAM including a local bit line LBL, a global bit line GBL, a local sense amplifier 10 and a global sense amplifier 11. In the configuration of Patent Reference 1, data stored in a 1T1C type memory cell MC is read out to the local bit line LBL and is transmitted from the local bit line LBL to a node Ns via a charge transfer gate Q1. In a read operation, a signal voltage of the node Ns is amplified by a transistor Q3 and thereafter is transmitted through the global bit line GBL and amplified by the global sense amplifier 11. In contrast, in a refresh operation of the DRAM, after the signal is transmitted along the same path, the signal latched in the global sense amplifier 11 is transmitted through the global bit line GBL and the local bit line LBL, and data is restored into the memory cell MC.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2010-055730 (U.S. Pub. No. 2010/0061170 A1)    [Patent Reference 2] Japanese Patent Application Laid-open No. H1-96895    [Patent Reference 3] Japanese Patent Application Laid-open No. H4-30385 (U.S. Pat. No. 5,361,233)    [Patent Reference 4] Japanese Patent Application Laid-open No. H7-235180    [Non-Patent Reference 1] T. Mano, et al., “Circuit Technologies for 16 Mb DRAMs,” ISSCC Dig. of Tech. Papers, PP. 22-23, February 1987.
In general, charge/discharge currents of bit lines and currents flowing in circuits in the memory cell array provide a large ratio of consumption current in the refresh operation. Then, in the conventional hierarchical memory cell array, the paths for restoring the data includes both the local bit line and the global bit line, as described above, and thus a non-negligible amount of current is required for the charge/discharge currents and for operations of sense amplifiers. With miniaturization in process and large capacity of the memory cell array in recent days, when it is required to shorten a refresh cycle in the refresh operation and to increase the number of word lines being simultaneously selected, particularly, there arises a serious problem of an increase in the consumption current in the refresh operation.
Further, the semiconductor device with the hierarchical bit line structure is normally configured so that the wiring pitch of the local bit lines is equal to that of the global bit lines. In this regard, conventionally a configuration has been known in which the wiring pitch of the global bit lines is broadened compared with that of the local bit lines. For example, Patent References 2, 3 and Non-Patent Reference 1 disclose techniques capable of restoring data stored in the memory cell through the local bit line in a state of not being connected to the global sense amplifier by providing a local sense amplifier having a restoring function. By applying such techniques, it is possible to broaden the wiring pitch of the global bit lines and to reduce the number of global sense amplifiers. However, according to the techniques, since the local sense amplifiers are configured using latch type differential amplifiers, an increase in chip area due to the area occupied by the local sense amplifiers is inevitable. As a measure against this problem, Patent Reference 4 discloses a technique employing a configuration in which a pair of local sense amplifiers composed of only NMOS transistors can be selectively connected to a plurality of local bit lines so that the occupied area and the number or the local sense amplifiers can be reduced. However, in this configuration, when the data stored in the memory cell is read out to the local bit line, the restoring operation is not performed for local bit lines that are not connected to the global sense amplifier via the local sense amplifiers, and there arises a problem that the data of the memory cell is destructed.